Design Verification Engineer (Verilog) – ALTROCKS TECH PTE. LTD. in Punggol, Singapore
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Company ALTROCKS TECH PTE. LTD. is offering job opportunities for the position of Design Verification Engineer (Verilog) in the Punggol area. The job type available is Full-time.
We are looking for candidates who possess skills with beginners/seniors experience. We value honesty, discipline, and responsibility in our employees.
ALTROCKS TECH PTE. LTD. operates in the (according to the company) industry. If you are interested in applying to this company, please proceed with your application.
Job Information
| Company: | ALTROCKS TECH PTE. LTD. |
| Position: | Design Verification Engineer (Verilog) |
| Region: | Punggol, Singapore |
| Education: | Confidential |
| Salary: | SGD 6.000 - SGD 9.000 per Month |
| Job Type: | Full-time |
Job Description
Experience: 5 years & above
- Experience in IP Level & SOC Level Verification.
- Skilled in Verilog, SystemVerilog, UVM.
- High Experience in defining block, Sub-System, and SOC top level test plans.
- Experienced with System Verilog assertions, code, and functional coverage implementation and analysis.
- Experience with one or more high-speed protocols is an added advantage.
- Good interpersonal and communication skills.
Company: ALTROCKS TECH PTE. LTD.
Benefit
- Overtime bonus
- Gaining experience
- Comfortable work environment
Application Requirements
- Physically and mentally healthy
- Minimum age of 17 years
- Disciplined and punctual
- Honest and responsible
- Good personality
- Enthusiasm in working and learning
- For other requirements, please check through the job form.
Company address
| Province | Singapore |
| City | Punggol |
| Full Address | 3 Ang Mo Kio Street 62, #06-19 Altrocks Tech Pte Ltd, Link@AMK 569139 |
| Google Map | Google Map |
Job Application Information
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